The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jul. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Malek Musleh, Portland, OR (US);

Tony Hurson, Austin, TX (US);

Pedro Yebenes Segura, San Jose, CA (US);

Allister Alemania, North Plains, OR (US);

Roberto Penaranda Cebrian, Santa Clara, CA (US);

Ayan Banerjee, Bengaluru, IN;

Robert Southworth, Chatsworth, CA (US);

Sujoy Sen, Beaverton, OR (US);

Curt E. Bruns, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 49/90 (2022.01); G06F 15/173 (2006.01); H04L 47/762 (2022.01); H04L 47/78 (2022.01); H04L 47/80 (2022.01);
U.S. Cl.
CPC ...
H04L 49/90 (2013.01); G06F 15/17331 (2013.01); H04L 47/762 (2013.01); H04L 47/781 (2013.01); H04L 47/805 (2013.01);
Abstract

Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on expected length of runtime of the connection and the expected length of runtime of the connection.


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