Memory device including error logging device and operating methods thereof

Abstract

A memory device includes a memory cell array including memory cells coupled to a plurality of rows that are subject to error check operations. A fault detection circuit generates a fault address for each of the plurality of rows according to a result of an error check operation and outputs the fault addresses together with a fault input signal to a fault information management circuit. The fault information management circuit uses the fault addresses to generate and store first to third fault addresses, where the first fault address is a start fault address. The start fault address and the second and third fault addresses are compared and used to generate fault mode information that defines a relationship between the stored start fault address and the second and third fault addresses, according to the fault input signal. The fault information management circuit outputs error information including the start fault address and the fault mode information.