Circuitry and methods for implementing forward-edge control-flow integrity (fecfi) using one or more capability-based instructions

Abstract

Techniques for implementing forward-edge control-flow integrity (FECFI) using capability instructions in a hardware processor are described. In certain examples, a hardware processor (e.g., core) includes a capability management circuit to check a capability for a memory access request for a memory, the capability comprising an address field and a bounds field that is to indicate a lower bound and an upper bound of an address space to which the capability authorizes access; a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction comprising: a first capability to indicate a first call table comprising a respective entry for each of a plurality of functions of a first type, a field to indicate a first offset of a first entry for a first function requested for execution, and an opcode to indicate the capability management circuit is to perform a first check that the first offset is within a lower bound and an upper bound of the first capability and a second check that the first offset is a permitted offset for the entries in the first call table, and in response to the first check and the second check both passing, cause an execution circuit to execute the first function; and the execution circuit to execute the decoded single instruction according to the opcode.