The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Nov. 21, 2024
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Surender Kumar, Noida, IN;

Pradip Singh, Noida, IN;

Fabrice Poulard, Houilles, FR;

Stefan Doll, Munich, DE;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 11/263 (2006.01);
U.S. Cl.
CPC ...
G06F 11/263 (2013.01);
Abstract

A system and method include receiving, by a security controller of a system-on-chip and from a controller of the system-on-chip, an indication that a debugger computing device is connected to a debug port of the system-on-chip. A user debug authorization key and a user debug profile are received and verified by the security controller. The user debug profile identifies a set of requested resources. A configuration of the system-on-chip is modified to allow the debugger computing device to access resources of the set of requested resources.


Find Patent Forward Citations

Kumar, Surender. (2026). Secure debug access of a system-on-chip device (U.S. Patent No. 12754812). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12754812

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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