The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Sep. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Seunghyun Baik, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/30 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/117 (2026.01); H10W 72/387 (2026.01); H10W 74/15 (2026.01); H10W 90/24 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes a substrate, a first semiconductor chip on an upper surface of the substrate, and electrically conductive bumps extending between and electrically connected to the substrate and the first semiconductor chip. A non-conductive film layer is provided, which has at least a portion extending between the electrically conductive bumps. A second semiconductor chip is provided, which extends on the upper surface of the substrate. Electrically conductive wires are provided that electrically connect respective portions of the second semiconductor chip to respective portions of the upper surface of the substrate. In addition, the upper surface of the substrate includes a dam, which protrudes between one of: (i) a region overlapping the second semiconductor chip, and (ii) a region connected to the wires and a region overlapping the first semiconductor chip. The upper surface of the substrate may also include a trench recessed alongside at least a portion of the dam.


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Baik, Seunghyun. (2026). Packaged integrated circuit devices with enhanced dam structures that provide increased yield and reliability (U.S. Patent No. 12751338). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12751338

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