Semiconductor device and manufacturing method thereof

Abstract

A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.