Low cross-talk noise resistive memory devices on a soi substrate and methods of making the same

Abstract

A semiconductor structure may include a semiconductor-on-insulator (SOI) substrate having a top semiconductor layer and a buried insulating layer. At least one moat trench may extend through the top semiconductor layer and the buried insulating layer and may laterally surround a first device region. A deep trench isolation structure may be formed within the moat trench and may include a non-insulating moat structure. A resistive memory array may be formed within the first device region, and peripheral devices may be formed outside the first device region. A metallic moat structure may laterally surround the resistive memory array. Upper-level metal interconnect structures may extend over the metallic moat structure and may electrically couple the peripheral devices to the resistive memory array.