The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jun. 12, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yejin Park, Suwon-si, KR;

Seung Yoon Kim, Suwon-si, KR;

Heesuk Kim, Suwon-si, KR;

Hyeongjin Kim, Suwon-si, KR;

Sehee Jang, Suwon-si, KR;

Minsoo Shin, Suwon-si, KR;

Seungjun Shin, Suwon-si, KR;

Sanghun Chun, Suwon-si, KR;

Jeehoon Han, Suwon-si, KR;

Jae-Hwang Sim, Suwon-si, KR;

Jongseon Ahn, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 80/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 80/00 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01); H10W 90/00 (2026.01); H10W 90/297 (2026.01);
Abstract

Disclosed are semiconductor devices, electronic systems including the same, and methods of fabricating the same. The semiconductor device comprises a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other, a memory channel structure including a first memory portion that penetrates the first gate stack structure, a through contact including a first through portion at a level the same as a level of the first memory portion, and a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion. A minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion.


Find Patent Forward Citations

Loading…