Techniques to mitigate drift in bias voltages

Abstract

A memory device includes a resistor string digital to analog convertor (DAC) configured to supply one or more offset voltages to a decision feedback equalizer (DFE) based on high and low bias voltages. The memory device also includes bias voltage generation circuitry configured to generate a reference current based on an offset voltage range trim, to generate a first correction current based on a detected temperature change, generate a second correction current based on a supplied voltage, the reference voltage of the memory device, and a supply correction trim, to generate an adjusted reference current based on the reference current, the first correction current, and the second correction current, to generate the high bias voltage based on the adjusted reference current, to generate the low bias voltage based on the reference current, and to supply the high bias voltage and the low bias voltage to the resistor string DAC.