Successive-approximation analog-to-digital converter

Abstract

The present invention aims to suppress an increase in the size of a circuit configuration and achieve speed-up. The present invention is a successive-approximation ADC including: a CDAC consisting of a main capacitor bank consisting of a plurality of first capacitors and an auxiliary capacitor bank including a plurality of second capacitors to supply a corrected capacitance value to the first capacitors, a comparator configured to output a bit signal based on a capacitance redistribution signal output according to capacitance redistribution by the CDAC in response to an analog input signal, a logic circuit configured to output a digital output signal based on the bit signal, and a corrected capacitance value designation circuit configured to output a correction designation value that designates a corrected capacitance value to be supplied to the first capacitors. The corrected capacitance value designation circuit holds in advance two correction designation values before 1 bit as pre-correction designation values, selects one of the pre-correction designation values according to the bit signal from the comparator, and calculates two most recent correction designation values based on the bit signal.