The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Nov. 19, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Heechan Lee, Suwon-si, KR;

Suyong Kim, Suwon-si, KR;

Suchang Jeon, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/3459 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory device includes control logic configured to control memory cell planes based on a determination result, wherein the control logic is further configured to, in response to the determination result for a first program loop in which a first memory cell plane is determined to be program-passed and a second memory cell plane is determined to be program-failed through a first verify voltage for a first program state, control the memory cell planes so that a number of times the verify operation of the first memory cell plane is performed is different from a number of times the verify operation of the second memory cell plane is performed in a second program loop performed sequentially after the first program loop.


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