3d memory block having low-resistance source/drain buried layer stacked architecture

Abstract

The present disclosure provides a memory block, a memory cell, and a manufacturing method of a memory block. The memory block includes a memory array, including: a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction; wherein each column of stacked strip structure extends along a column direction and comprises at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction. Each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure comprises a low-resistance conductive structure.