Wordline-coupled differential programming of two-terminal memory with increased cell density and consistent cell pitch

Abstract

An architecture is provided for differential programming of multiple one-resistor, one-transistor (1T1R) two-terminal resistive switching memory cells that define a single bit (e.g., a differential bit). The single bit can be a physical unclonable function (PUF) bit or a random number generation (RNG) bit, or the like. A program voltage can be applied concurrently to the multiple 1T1R cells on a common bitline, and a pass transistor activated to electrically short second terminals of the two-terminal resistive switching memory cells. As a result, programming of one of the multiple memory cells can intrinsically and very rapidly suppress programming of remaining memory cells of the differential bit, and greatly mitigate or avoid an invalid data result. In addition, two-terminal resistive switching memory cells of the architecture can have uniform or substantially uniform pitch there between, increasing cell density and minimizing or avoiding process and electrical variation among such memory cells.