The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jul. 19, 2022
Applicant:

National Tsing Hua University, Hsinchu, TW;

Inventors:

Ya-Chin King, Hsinchu, TW;

Hsin-Yuan Yu, Hsinchu, TW;

Chrong-Jung Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G11C 11/54 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10B 63/30 (2023.02); H10N 70/24 (2023.02); H10N 70/253 (2023.02); G11C 13/0007 (2013.01); G11C 13/003 (2013.01); G11C 2213/79 (2013.01);
Abstract

A high density embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer and a memory transistor. The select transistor is disposed on the semiconductor substrate and includes a first gate structure, a drain region and a source region. The drain region and the source region are located on the opposite sides of the first gate structure. The metal layer is connected to the drain region. The memory transistor is disposed on the semiconductor substrate and includes a second gate structure, a first electrode region, a second electrode region, a first memristor and a second memristor. The second gate structure is connected to the metal layer. The first memristor is formed between the second gate structure and the first electrode region. The second memristor is formed between the second gate structure and the second electrode region.


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