Error-correcting and error-detecting parity-check matrix to store a known bad data bit in a memory system

Abstract

A system includes: an error correction code (ECC) memory controller configured to read data stored in a memory, the data including a read codeword including system data and parity data, the ECC memory controller including an ECC decoder configured to: compute a syndrome based on the read codeword using a parity-check matrix including a plurality of columns, wherein a first group of syndromes calculated by the parity-check matrix in a case where the read codeword has a double-bit error and a virtually stored known bad data bit is set and a second group of syndromes calculated by the parity-check matrix in a case where the read codeword has a single-bit error or zero errors are disjoint; and in a case where the read codeword received has a double bit error and a virtually stored known bad data bit, detect an error and output an indication of detection of the error.