The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Nov. 02, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jongpa Hong, Suwon-si, KR;

Yeongkwon Ko, Suwon-si, KR;

Gunho Chang, Suwon-si, KR;

Wonkeun Kim, Suwon-si, KR;

Wonyoung Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 80/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/111 (2026.01); H10W 72/0198 (2026.01); H10W 72/07353 (2026.01); H10W 72/334 (2026.01); H10W 72/926 (2026.01); H10W 74/15 (2026.01); H10W 80/721 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01);
Abstract

A semiconductor package includes a base chip, a first semiconductor chip on the base chip, the first semiconductor chip including first through-vias, first bump structures on the first front surface of the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, the plurality of second semiconductor chips including second through-vias, adhesive layers respectively on the second front surfaces of the plurality of second semiconductor chips, and an encapsulant between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips. The adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip.


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