The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 05, 2022
Applicant:

Winbond Electronics Corp., Taichung City, TW;

Inventors:

Shou-Chi Tsai, Tainan City, TW;

Kai Jen, Taichung City, TW;

Assignee:

Winbond Electronics Corp., Taichung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/66 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 64/667 (2025.01); H10D 64/01 (2025.01);
Abstract

A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first work function layer, a second work function layer, a protective layer, a gate stack, a first liner, a second liner, a planarization layer, and a gate plug. The first work function layer is disposed on a substrate. The second work function layer is disposed on the first work function layer. The protective layer is disposed on the second work function layer. The gate stack is disposed on the protective layer. The first liner is disposed on the gate stack. The second liner is disposed on the first liner. The planarization layer is disposed on the second liner. The gate plug is disposed on the planarization layer and in contact with the first work function layer and the second work function layer.


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