The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 02, 2024
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Ronak Prakashchandra Trivedi, Cupertino, CA (US);

Hanqing Xing, Cupertino, CA (US);

Jean Cauxuan Le, Santa Clara, CA (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1038 (2013.01); H03M 1/1071 (2013.01); H03M 1/06 (2013.01); H03M 1/1023 (2013.01); H03M 1/1028 (2013.01);
Abstract

The disclosure relates to self-calibration of non-linearity in a digital to analog converter (DAC). Example embodiments include a method for calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the method comprising: providing first calibration input digital signals to a thermometric weighted segment and measuring first outputs of the DAC with an ADC; providing second calibration input digital signals to the thermometric weighted segment and measuring second outputs of the DAC with the ADC; calculating a first scaling factor for first switches and resistive elements by dividing each of the second outputs of the DAC by a difference between adjacent ones of the first outputs of the DAC; calculating a second scaling factor for second switches from a sum of the first outputs of the DAC divided by a measured output range of the DAC; and storing the first and second scaling factors in a memory module.


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