The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

May. 28, 2024
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Xiang Yang, Santa Clara, CA (US);

Muhammad Masuduzzaman, Chandler, AZ (US);

Deepanshu Dutta, Fremont, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G06F 17/16 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G06F 17/16 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01);
Abstract

A non-volatile storage apparatus programs memory cells, including performing program-verify. The performing program-verify comprises applying location dependent bit line voltages to the bit lines connected to the memory cells. The location dependent bit line voltages are different in voltage magnitude for different locations based on distance from bit line drivers connected to the bit lines. The memory cells are read by applying, regardless of location, a common bit line voltage to the bit lines that is higher in voltage magnitude than the any of the location dependent bit line voltages. In one example implementation, the read process is used to perform in-memory vector-matrix multiplication.


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