The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 05, 2024
Applicant:

Neo Semiconductor, Inc., San Jose, CA (US);

Inventor:

Fu-Chang Hsu, San Jose, CA (US);

Assignee:

NEO Semiconductor, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06N 3/063 (2023.01); G11C 16/26 (2006.01); H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01); H10B 51/20 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10B 63/10 (2023.01); H10B 69/00 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G06N 3/063 (2013.01); G11C 16/26 (2013.01); H10B 12/20 (2023.02); H10B 41/20 (2023.02); H10B 43/20 (2023.02); H10B 51/20 (2023.02); H10B 61/20 (2023.02); H10B 63/10 (2023.02); H10B 63/84 (2023.02); H10B 69/00 (2023.02);
Abstract

Various 3D cells, array structures, and processes are disclosed. In an embodiment, a memory cell array structure is provided that includes memory cells organized into rows and columns, input lines where each input line is connected to memory cells in a selected row, and the input lines form input line groups, and output lines where each output line is connected to memory cells in a selected column, and the output lines form output line groups. The array structure also includes a multiplexer having multiplexer inputs and multiplexer outputs such that the multiplexer inputs are connected to the output line groups, neuron circuits connected to the multiplexer outputs, and the memory cell array simulates a neural network in which the input lines simulate input layer neurons of the neural network, and the output lines simulate output layer neurons of the neural network.


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