The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Dec. 21, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jiyun Li, Boise, ID (US);

Yuan He, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01);
Abstract

Memory devices including tri-state memory cells are disclosed. A memory device may include a first tri-state cell that may store a first voltage level that is one of three voltage levels, a second tri-state cell that may store a second voltage level that is one of the three voltage levels, and three input/output lines that may access the memory device. The three input/output lines may carry three respective binary signals based on the first voltage level and the second voltage level. A memory device may include a bank including a number of continuous arrays of tri-state memory cells. Each of the tri-state memory cells may be accessible by a respective bit line. Groups of the bit lines may be associated with respective column-select lines. The bank may include a number of sub-word-line drivers interspersed between the number of continuous arrays. Associated systems and methods are also disclosed.


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