The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2026

Filed:

Jun. 07, 2023
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Vinod Inipodu Murugan, San Jose, CA (US);

Anirudha Shelke, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01);
Abstract

A controller iteratively activates a control signal for one-half a clock cycle while sweeping its phase relationship to the rising edge of the clock. Phase relationships that result in the rising edge of the clock occurring while the control signal is active result in the memory device outputting command/address data on the data bus. Phase relationships that do not result in the rising edge of the clock occurring while the control signal is active do not result in the memory device outputting the command/address data on the data bus. By changing the data on the CA bus between activations of the control signal, the controller can ascertain what phase relationships result in the control signal being successfully sampled. From this information, the controller can select a reliable setting for the phase relationship between the control signal and the clock signal.


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