The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
Nov. 20, 2023
Method for managing the isolation of resources of a system-on-chip, and corresponding system-on-chip
Applicant:
Stmicroelectronics (Grand Ouest) Sas, Le Mans, FR;
Inventor:
Loic Pallardy, Rouillon, FR;
Assignee:
STMicroelectronics (Grand Ouest) SAS, Le Mans, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0772 (2013.01); G06F 11/0745 (2013.01);
Abstract
The system-on-chip includes at least one master device, at least one slave resource, an interconnection bus including an error notification channel, and a resource isolation system including, for each resource, a protection circuit configured to block or transmit transactions addressed to the resource via the interconnection bus, according to access rights of the resource and the transaction. The protection circuit is capable of generating a notification signal on the error notification channel of the interconnection bus in case of blockage of a transaction.