The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Apr. 27, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joonghyun Baek, Suwon-si, KR;

In Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/50 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 72/07554 (2026.01); H10W 72/5445 (2026.01); H10W 72/865 (2026.01); H10W 72/877 (2026.01); H10W 72/879 (2026.01); H10W 72/884 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/752 (2026.01); H10W 90/753 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor package includes: a substrate that includes a wiring circuit; an interposer on the substrate, wherein the interposer includes a first side and a second side opposing each other and a third side and a fourth side between the first side and the second side, and wherein the interposer includes an interconnect circuit electrically connected to the wiring circuit; a first and second buffer chips on the interposer; a first chip stack adjacent to the first side of the interposer and connected to the first buffer chip; a second chip stack adjacent to the second side of the interposer and connected to the second buffer chip; a third chip stack adjacent to the third side of the interposer, and wherein the third chip stack includes first and second groups of semiconductor chips, which are electrically connected to the first and second buffer chips, respectively, via the interconnect circuit.


Find Patent Forward Citations

Quick Actions:

Baek, Joonghyun. (2026). Semiconductor package (U.S. Patent No. 12740482). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12740482

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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