The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Aug. 15, 2022
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Daehan Youn, Suwon-si, KR;
Kyoungmin Lee, Yongin-si, KR;
Junho Huh, Yongin-si, KR;
Heeseok Lee, Suwon-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); G11C 5/14 (2006.01); H10W 72/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); G11C 5/147 (2013.01); H10W 72/823 (2026.01); H10W 90/291 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract
Provided are a system on chip (SoC) having a three-dimensional (3D) chiplet structure, and an electronic device including the SoC. The electronic device includes a printed circuit board, the SoC on the printed circuit board, and a memory device on the SoC, wherein the SoC includes an SoC package substrate, a first die arranged on the SoC package substrate, and having a logic circuit thereon, and a second die arranged on the first die, and having a logic circuit thereon.