Semiconductor packages having conductive patterns including wiring patterns and under-bump patterns, and methods of fabricating the same

Abstract

Disclosed are semiconductor packages and fabrication methods thereof. The semiconductor package may include a lower substrate, a lower semiconductor chip, a redistribution layer, an upper semiconductor chip, and a through electrode. The lower substrate may include a first dielectric layer, a first conductive pattern having a wiring pattern and an under-bump pattern, a second dielectric layer, and a second conductive pattern. The under-bump pattern may include a first head part and a first tail part. The first head part may have a first lateral surface on the first dielectric layer that is inclined to a top surface of the first dielectric layer. The second conductive pattern may have a second lateral surface on the second dielectric layer that is perpendicular to a top surface of the second dielectric layer.