The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

May. 25, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kristof Darmawikarta, Chandler, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Haobo Chen, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10P 72/70 (2026.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10P 72/743 (2026.01); H10W 90/724 (2026.01);
Abstract

A via structure for an embedded component and method for making same. The via structure includes a pillar of conductive material perpendicularly attached to a surface of a build-up dielectric layer. The surface and the pillar are conformally covered by a film layer. The film layer is conformally applied and retains a feature landscape profile. A dielectric layer is located on the film layer, the dielectric layer has an upper dielectric surface that is planar. The pillar has a top that is exposed at the upper dielectric surface. The film layer can act as a barrier to cracking because it is selected to have a higher hardness than the material making up the dielectric layer.


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