The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Oct. 16, 2023
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Yuichi Onozawa, Matsumoto-city, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 14/60 (2026.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 8/50 (2025.01); H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/53 (2025.01); H10D 62/60 (2025.01); H10D 62/834 (2025.01); H10P 34/40 (2026.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10P 14/6539 (2026.01); H10D 8/045 (2025.01); H10D 8/411 (2025.01); H10D 8/50 (2025.01); H10D 12/032 (2025.01); H10D 12/038 (2025.01); H10D 12/441 (2025.01); H10D 12/481 (2025.01); H10D 62/106 (2025.01); H10D 62/393 (2025.01); H10D 62/53 (2025.01); H10D 62/60 (2025.01); H10D 62/605 (2025.01); H10D 62/834 (2025.01); H10P 14/6506 (2026.01); H10P 34/40 (2026.01); H10D 64/111 (2025.01); H10D 64/112 (2025.01);
Abstract

A semiconductor device, including: a semiconductor substrate having first and second main surfaces, and an n-type drift layer therein; a p-type layer provided between the first main surface and the drift layer; and an n-type high-concentration layer provided between the second main surface and the drift layer, and including a plurality of buffer layers. A carrier concentration of the semiconductor device is higher in the n-type high-concentration layer than in the semiconductor substrate. In one of the buffer layers, the carrier concentration decreases both upward and downward in a depth direction of the semiconductor device, from a peak concentration thereof at a peak position to a pre-determined concentration at first and second depth positions respectively above and below the peak position. In the depth direction, a distance between the first depth position and the peak position is larger than a distance between the peak position and the second depth position.


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