The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Mar. 31, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Tsing Hua University, Hsinchu City, TW;

Inventors:

Yung-Chun Wu, Hsinchu City, TW;

Yi-Ju Yao, New Taipei City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/014 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

A method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately arranged over the semiconductor substrate, wherein the first semiconductor layers have a lower germanium concentration than a germanium concentration of the second semiconductor layers; patterning the epitaxial stack into a fin; forming a gate structure over a channel region of the fin, wherein the gate structure is in contact with the first semiconductor layers and the second semiconductor layers within the channel region of the fin; and forming source/drain regions on opposite sides of the channel region of the fin.


Find Patent Forward Citations

Wu, Yung-Chun. (2026). Semiconductor device and manufacturing method thereof (U.S. Patent No. 12740100). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12740100

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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