The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Oct. 18, 2024
Applicant:

Stmicroelectronics International N.v., Plan-les-Ouates, CH;

Inventors:

Matteo Colombo, Monza, IT;

Augusto Andrea Rossi, Pavia, IT;

Jerome Deroo, Rives sur Fures, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/085 (2006.01); H04L 7/033 (2006.01); H04L 7/04 (2006.01);
U.S. Cl.
CPC ...
H04L 7/005 (2013.01); H03L 7/085 (2013.01); H04L 7/0331 (2013.01); H04L 7/048 (2013.01);
Abstract

An electronic digital system includes a digital core and a Serializer Deserializer module. A FIFO device of the core reads and writes on a set of buses coupled to said Serializer Deserializer module. The Serializer Deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signals transmitted by transmitters. The serial signals and corresponding transmitters are logically grouped. The transmitters include PLL circuits generating PLL clocks, using as reference a cluster transmitter reference clock common, to a respective cluster of transmitters controlling a frequency of serialization operation and low frequency clocks obtained by the PLL clocks according to one or more groups corresponding to group of buses.


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