The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Oct. 08, 2024
Synopsys, Inc., Sunnyvale, CA (US);
Shailesh Kumar Chauhan, Uttar Pradesh, IN;
Akhil Thotli, Karnataka, IN;
Kailash Kumar, Uttar Pradesh, IN;
Ankit Agrawal, Uttar Pradesh, IN;
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
Failsafe IO circuitry is provided that can operate in a failsafe mode and a normal mode. The failsafe IO circuitry can include input circuitry that (i) receives a pad signal (PAD) from driver circuitry, (ii) receives control signals (VDDIO, VREFN) and (iii) provides an output signal (PADBY) generated based on the received control signals (VDDIO, VREFN), wherein, when operating in a normal mode, the pad signal (PAD) is a floating signal and the output signal (PADBY) is 0 volts (0V), and power gated logic circuitry that (i) receives the output signal (PADBY) from the input circuitry, (ii) receives the control signals (VDDIO, VREFN) and (iii) outputs a reference pad failsafe signal (PAD_FS), wherein, when operating in the normal mode, the reference pad failsafe signal (PAD_FS) is 0V.