The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2026
Filed:
Jun. 09, 2023
Qualcomm Incorporated, San Diego, CA (US);
Gokce Sarar, San Diego, CA (US);
Ryan Michael Carey, Nashua, NH (US);
Arnav Ballani, San Diego, CA (US);
Bernard Bouron, Sunnyvale, CA (US);
Chandram Kotturi, San Diego, CA (US);
Chin-Wei Hsu, Zhubei City, TW;
Akshay Sanjay Sarode, Pune, IN;
Romain Lepert, Amsterdam, NL;
Michael Defferrard, Chavannes-sous-Orsonnens, CH;
Onur Atan, San Diego, CA (US);
Lindsey Makana Kostas, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Certain aspects of the present disclosure provide techniques and apparatus for evaluating electronic circuit designs. A directed graph representing a netlist design for an electrical circuit is accessed, the netlist design comprising a plurality of electronic components and a plurality of connections among the plurality of electronic components. A node in the directed graph is selected, the node corresponding to a register that receives input from one or more of the plurality of electronic components in the netlist design. A subgraph is generated for the node, based on the directed graph, comprising identifying a connectivity cone ending at the first register. A functional embedding is generated for the subgraph based on a trained encoder machine learning model. A predicted performance characteristic of the netlist design is generated based at least in part on the functional embedding.