The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2026

Filed:

Mar. 13, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilles Pokam, Livermore, CA (US);

Andre Seznec, Acigne, FR;

Jared Warner Stark, IV, Portland, OR (US);

Bhargav Reddy Godala, Princeton, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/126 (2016.01); G06F 9/38 (2018.01); G06F 12/12 (2016.01);
U.S. Cl.
CPC ...
G06F 12/126 (2013.01); G06F 9/3802 (2013.01); G06F 12/12 (2013.01);
Abstract

Techniques and mechanisms for prioritizing entries of a processor resource which is accessed to facilitate the fetching of an instruction for execution. In an embodiment, a first entry of the resource includes, or otherwise corresponds to, a version of the instruction. The first entry is prioritized based on an event wherein the instruction is retired from execution after a front end stall which is due to the instruction. While the first entry is prioritized, the entry is protected from a selection to be evicted from the resource. In another embodiment, second entries of a cache are variously prioritized, based on respective retirement events, to be available for instruction prefetching.


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