The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Apr. 04, 2022
Qualcomm Incorporated, San Diego, CA (US);
Stanley Seungchul Song, San Diego, CA (US);
Jonghae Kim, San Diego, CA (US);
Je-Hsiung Lan, San Diego, CA (US);
Periannan Chidambaram, San Diego, CA (US);
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
Three-dimensional (3D) integrated circuit (IC) (3DIC) package employing a redistribution layer (RDL) interposer facilitating semiconductor die ('die'), and related fabrication methods. The 3DIC package includes an RDL interposer that has one or more RDL metallization layers formed adjacent to a first, bottom die(s). A second, top die(s) is stacked on the RDL interposer. The RDL interposer provides an extended die area that the top die can be coupled so that the fabrication process of the 3DIC package is independent die sizes. The bottom die(s) can be singulated and disposed in an RDL metallization layer(s) as part of a reconstituted RDL interposer regardless of whether the top die(s) is greater than or less than the size of the bottom die(s). Also, the RDL interposer being the substrate in which the bottom die(s) is disposed and top die(s) is coupled provides efficient signal routing paths to the top and bottom dies.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile