The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jun. 08, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kristof Kuwawi Darmawikarta, Chandler, AZ (US);

Benjamin T. Duong, Phoenix, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Thomas Sounart, Chandler, AZ (US);

Aleksandar Aleksov, Chandler, AZ (US);

Adel A. Elsherbini, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H10D 1/68 (2025.01); H10W 42/00 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 42/00 (2026.01); H10D 1/692 (2025.01); H10W 70/611 (2026.01); H10W 70/614 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/141 (2026.01); H10W 74/147 (2026.01); H10W 90/00 (2026.01); H10W 72/823 (2026.01); H10W 90/293 (2026.01); H10W 90/701 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01);
Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die in a first dielectric layer; and a capacitor including a first conductive pillar and a second conductive pillar in the first dielectric layer, each pillar having a first end and an opposing second end, where the first and second conductive pillars form a first plate of the capacitor; a second dielectric layer on the die and on the second end of the first and second conductive pillars extending at least partially along a first thickness of the first and second conductive pillars and tapering from the second end towards the first end; and a metal layer on the second dielectric layer, wherein the metal layer extends at least partially along a second thickness of the first and second conductive pillars, where the metal layer forms a second plate of the capacitor.


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