The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jul. 27, 2023
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Mark D. Kraman, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

James Kai, Santa Clara, CA (US);

Koichi Matsuno, Fremont, CA (US);

Jixin Yu, Milpitas, CA (US);

Ruogu Matthew Zhu, San Jose, CA (US);

Seyyed Ehsan Esfahani Rashidi, Milpitas, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/10 (2023.01); G11C 16/04 (2006.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10W 20/42 (2026.01);
Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.


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