The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
May. 31, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 72/00 (2026.01); H10P 74/20 (2026.01); H10P 76/20 (2026.01); H10P 76/40 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 74/00 (2026.01);
U.S. Cl.
CPC ...
H10P 72/0616 (2026.01); H10P 74/203 (2026.01); H10P 76/2041 (2026.01); H10P 76/4085 (2026.01); H10W 74/114 (2026.01); H10W 90/701 (2026.01); H10W 72/01304 (2026.01); H10W 72/01353 (2026.01); H10W 72/01355 (2026.01); H10W 72/07352 (2026.01); H10W 72/321 (2026.01); H10W 74/00 (2026.01); H10W 90/734 (2026.01);
Abstract
The present disclosure provides a method according to some embodiments. The method includes receiving an integrated circuit (IC) layout of a semiconductor structure that includes a redistribution layout (RDL) structure having a plurality of RDL metallic features; modifying the IC layout such that the modified RDL structure meets a criterion associated with a X-Y ratio gap; generating a tape-out according to the modified IC layout; and fabricating the semiconductor structure according to the modified IC layout defined in the tape-out.