The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Apr. 09, 2021
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Tetsuo Takahashi, Tokyo, JP;

Hidenori Fujii, Tokyo, JP;

Shigeto Honda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/861 (2006.01); H10D 8/00 (2025.01); H10D 12/00 (2025.01); H10D 64/00 (2025.01); H10D 84/00 (2025.01); H10D 84/60 (2025.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H10D 84/617 (2025.01); H10D 8/422 (2025.01); H10D 12/481 (2025.01); H10D 64/117 (2025.01); H10D 84/144 (2025.01); H10D 84/161 (2025.01); H10D 84/611 (2025.01);
Abstract

According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region.


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