The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Feb. 17, 2023
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Peter Moens, Erwetegem, BE;

Balaji Padmanabhan, Chandler, AZ (US);

Dean E. Probst, West Jordan, UT (US);

Prasad Venkatraman, Gilbert, AZ (US);

Tirthajyoti Sarkar, Fremont, CA (US);

Gary Horst Loechelt, Tempe, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/668 (2025.01); H10D 30/0297 (2025.01); H10D 62/127 (2025.01); H10D 64/117 (2025.01);
Abstract

An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.


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