The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Sep. 01, 2023
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Kazuhiro Tamura, Kyoto, JP;

Naoki Izumi, Kyoto, JP;

Yusuke Shimizu, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2025.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 30/657 (2025.01); H10D 30/0281 (2025.01); H10D 62/153 (2025.01); H10D 62/157 (2025.01); H10D 62/393 (2025.01);
Abstract

A semiconductor device includes an n-type semiconductor layer, a p-type drift region formed in a surface layer portion of the semiconductor layer, an n-type body region formed in the surface layer portion of the semiconductor layer, a p-type drain region formed in a surface layer portion of the drift region, a p-type source region formed in a surface layer portion of the body region, a gate insulating film formed on a surface of the semiconductor layer, and a polysilicon gate formed on the gate insulating film, wherein a region extending from the source region to a side edge of the drift region is a channel region, and wherein the polysilicon gate includes a p-type first portion facing at least a portion of the channel region, and an n-type second portion facing at least a portion of the drift region.


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