The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jun. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventor:

En-Shuo Lin, New Taipei City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H01P 3/00 (2006.01); H01P 11/00 (2006.01); H10D 30/01 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10P 14/20 (2026.01); H10P 14/24 (2026.01); H10W 44/20 (2026.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H01P 3/003 (2013.01); H01P 11/003 (2013.01); H10D 30/015 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10P 14/24 (2026.01); H10P 14/2905 (2026.01); H10P 14/3216 (2026.01); H10P 14/3416 (2026.01); H10P 14/3418 (2026.01); H10P 14/3421 (2026.01); H10W 44/20 (2026.01); H10W 44/216 (2026.01);
Abstract

A semiconductor structure includes a substrate including a p-type region and an n-type region, wherein the n-type region is in the p-type region and a distance between a top surface of the substrate and the n-type region is less than a distance between the top surface of the substrate and the p-type region. A buffer layer is over the n-type region and a first III-V compound layer is over the buffer layer. A second III-V compound layer is over the first III-V compound layer and a metal structure is over the second III-V compound layer. The metal structure may include a coplanar waveguide or a high electron mobility transistor.


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