The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jun. 28, 2024
Applicant:

Sunrise Memory Corporation, San Jose, CA (US);

Inventors:

Eli Harari, Saratoga, CA (US);

Wu-Yi Henry Chien, San Jose, CA (US);

Scott Brad Herner, Portland, OR (US);

Assignee:

SUNRISE MEMORY CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 64/01 (2025.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 64/037 (2025.01); H10W 20/033 (2026.01); H10W 20/098 (2026.01);
Abstract

A NOR memory string formed by with a first conductor and a second conductor including first and second storage transistors sharing a common drain region and a common source region, the first conductor serving as gate electrode to the first storage transistor and the second conductor serving as gate electrode to the second storage transistor, each storage transistor having a channel region and a data storage layer provided between its gate electrode and its channel region, wherein the data storage layer of the first storage transistor surrounds its gate electrode, and the data storage layer of the second storage transistor does not surround its gate electrode with portions immediately adjacent the data storage layer of the first storage transistor. A dielectric barrier film between the data storage layers of the first and second storage transistors provides a discontinuity to prevent lateral conduction between the storage transistors.


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