Semiconductor structure comprising two vertical transistors and method for forming same

Abstract

The disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a storage array located on the substrate and including a plurality of memory cells arranged in an array along a first direction and a second direction, each memory cell including a transistor structure that includes a gate electrode and an active area that includes a first active area and a second active area distributed on opposite sides of the gate electrode along the first direction; a word line extending along the second direction, being continuously and electrically connected with a plurality of gate electrodes in the memory cells arranged at intervals along the second direction; a bit line extending along the first direction and located on outside of each of the memory cells along the second direction. The bit line is continuously and electrically connected with the first active area and the second active area in a plurality of the memory cells arranged at intervals along the first direction.