The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Jul. 25, 2023
Cadence Design Systems, Inc., San Jose, CA (US);
Edward Brown, Cranleigh, GB;
William Robert Reece, Over, GB;
Thomas Andrew Newton, Great Cambourne, GB;
Natarajan Viswanathan, Austin, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods and systems for performing route-based cell merging for a clock tree. The methods and systems access, from memory, a circuit design comprising a clock tree that interconnects a clock source to a plurality of clock sinks through a plurality of components. The methods and systems generate a Steiner tree that represents at least a portion of the clock tree including a portion of the plurality of components and identify two or more components of the portion of the plurality of components in the Steiner tree that are part of a direct fanout of a common node representing a set of components of the plurality of components. The methods and systems determine that the identified two or more components satisfy a mergeability function and, in response, modify at least a portion of the clock tree by merging the set of components into a single component.