The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2026

Filed:

Jan. 06, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Zengquan Wu, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/20 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/3323 (2020.01); G06F 30/20 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/367 (2020.01); G06F 30/396 (2020.01);
Abstract

A method for determining performance of sequential logic elements includes the following operations. To check a circuit, a performance check file corresponding to each of the sequential logic elements of the circuit is obtained; and the circuit is separately simulated to obtain the simulation result, by using a plurality of simulation waveforms, based on the performance check file corresponding to each of the sequential logic elements. The performance check file may be used to determine, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result.


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