Memory device and operation method thereof, memory system and memory controller

Abstract

According to one aspect, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M reference read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M reference read voltages in combination with a preset function model. The peripheral circuit may be configured to, based on the predicted valley voltage, determine a target valley voltage and the target valley voltage is configured as a read voltage used when a read operation is performed on the at least one code word.