The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

Mar. 28, 2024
Applicant:

Ap Memory Technology Corporation, Hsinchu County, TW;

Inventors:

Chung-Chiang Huang, HsinChu, TW;

Kee-Wei Chung, HsinChu, TW;

Ru-Yi Cai, HsinChu, TW;

Assignee:

AP Memory Technology Corporation, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/10 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/114 (2026.01); H10W 72/0198 (2026.01); H10W 72/072 (2026.01); H10W 72/07338 (2026.01); H10W 72/241 (2026.01); H10W 72/884 (2026.01); H10W 90/722 (2026.01); H10W 90/732 (2026.01); H10W 90/752 (2026.01);
Abstract

A semiconductor structure including a semiconductor die, a component layer and a pseudo static random access memory (PSRAM) die is provided. The component layer is disposed on the surface of the semiconductor die, wherein the component layer includes an organic layer. The PSRAM die is disposed on the surface of the semiconductor die and is electrically connected to the semiconductor die. A manufacturing method of a semiconductor structure is also provided.


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