The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Feb. 14, 2024
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Kishan Chanumolu, Bengaluru, IN;
Sandeep Dwivedi, Bengaluru, IN;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 72/00 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 72/072 (2026.01); H10W 72/075 (2026.01); H10W 72/9445 (2026.01); H10W 90/724 (2026.01); H10W 90/754 (2026.01);
Abstract
An apparatus includes a die with a first face, a second face opposite the first face, and a third face located between the first face and the second face, I/O cells coupled to the first face of a die, where the I/O cells are configured to be selectively bonded to a package by wirebonded interconnections at a first pitch or flip-chip interconnections at a second pitch that is larger than the first pitch, and a bond area including decoupling capacitors that is located between each I/O cell and the third face of the die.