The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2026

Filed:

May. 31, 2024
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Zeqing Shen, San Jose, CA (US);

Bo Qi, San Jose, CA (US);

Abhijit B. Mallick, Fremont, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10P 50/00 (2026.01); H10P 14/60 (2026.01); H10P 50/28 (2026.01);
U.S. Cl.
CPC ...
H10P 50/73 (2026.01); H10P 14/6334 (2026.01); H10P 14/6682 (2026.01); H10P 50/283 (2026.01);
Abstract

Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a microelectronic device is provided and includes a film stack disposed on a substrate and a patterned hard mask disposed on an upper surface of the film stack. The film stack has a stack thickness and contains a plurality of alternating layers of oxide layers and nitride layers. The microelectronic device also includes a plurality of openings having a depth disposed between a plurality of structures, each structure has a sidewall and each opening has a bottom, the depth is less than the stack thickness, and each opening has an aspect ratio of greater than 50 relative to the depth. The microelectronic device also includes an etch protection liner disposed on the patterned hard mask and the sidewalls.


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