The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2026
Filed:
Nov. 10, 2022
International Business Machines Corporation, Armonk, NY (US);
Albert M. Chu, Nashua, NH (US);
Brent A. Anderson, Jericho, VT (US);
Junli Wang, Slingerlands, NY (US);
Albert M. Young, Fishkill, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Carl Radens, LaGrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.